;; circuit2.clp: Jess code to represent a logic circuit ;; ;; Note: this is demonstration code only; ;; IT DOESN'T WORK! ;; ;; Modified from circuit1.clp; the idea was to separate the value ;; propagation from the structure so as to avoid the infinite loop ;; problem of circuit1.clp. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Circuit structure ;; ;; Each circuit element has a name and connectivity ;; information and a current value. ;; a NOT gate (deftemplate not-gate "Logical not" (slot name) (slot input) (slot output)) ;; Input port (deftemplate input-port "Circuit input" (slot name) (slot output)) ;; Output port (deftemplate output-port "Circuit output" (slot name) (slot input)) ;; Connector ;; Note that this really is unnecessary; we could just connect each ;; element directly (deftemplate connector "Connects one input to one or more outputs" (slot name) (slot input) (multislot output)) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Circuit activity ;; All elements have one value (deftemplate element-state "Activity of an element" (slot name) (slot value (default unknown))) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; A simple circuit (deffacts simple "A simple circuit" (input-port (name in1) (output conn1)) (connector (name conn1) (input in1) (output not1)) (not-gate (name not1) (input conn1) (output conn2)) (connector (name conn2) (input not1) (output out1)) (output-port (name out1) (input conn2)) (element-state (name in1) (value TRUE)) (element-state (name conn1)) (element-state (name not1)) (element-state (name conn2)) (element-state (name out2)) ) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Gate rules ;; This propagates an input value from an input port to a ;; connector. IT STILL DOESN'T WORK! Why? Well, it still modifies a ;; fact on its RHS that is matched by a CE on its LHS. The modified ;; fact is still matched by that CE, and nothing else is done to ;; prevent the other CEs on the LHS from being matched, so we get the ;; rule re-activated and have an infinite loop (defrule propagate-input "Copy value from input port to connector" (input-port (name ?n) (output ?c)) (element-state (name ?n) (value ?v&~unknown)) ?cf <- (element-state (name ?c)) => (modify ?cf (value ?v)))