Controlling interrupts is critical to the OS. If an interrupt occurs when the system isn’t prepared it can lose data or it’s context and crash.
The OS needs to be able to turn interrupts off and on so it can protect critical blocks of code. These are called Critical Sections.
On ARM interrupts are controlled by masking out or setting the F and I bits in the CPSR.
The CPSR has to be saved to register. The value in the register is then modified. Then the value is written back the CPSR.
Disabling interrupts:
MRS r0, cpsr
ORR r0, r0, #0x80
MSR cpsr_c, r0
Enabling interrupts:
MRS r0, cpsr
ORR r0, r0, #0x80
MSR cpsr_c, r0